Thin film transistor substrate and method of manufacturing the same

ABSTRACT

A thin film transistor (TFT) substrate having an improved wire structure without an under-cut phenomenon that may occur during formation of a gate wire having a double-layered structure and a method of manufacturing the same are provided, where the method includes forming a first metal layer made of at least one low resistance material selected from the group consisting of Al, AlNd, Cu, and Ag, forming a second metal layer made of at least one heat-resistant, etch-resistant material selected from the group consisting of Cr, CrNx, Ti, Mo, and MoW on the first metal layer, forming an etch mask on the second metal layer, sequentially etching the second metal layer and the first metal layer using the etch mask, and forming a second metal layer pattern and a first metal layer pattern, respectively, and selectively re-etching the second metal layer pattern using the etch mask to make a width of the second metal layer pattern smaller than or substantially equal to a width of the first metal layer pattern, and completing a gate wire.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Continuation of U.S. application Ser. No.11/455,450 filed on Jun. 19, 2006, which claims foreign priority under35 U.S.C. §119 to Korean Patent Application No. 10-2005-0055046, filedon Jun. 24, 2005 in the Korean Intellectual Property Office, thedisclosures of which are incorporated by reference herein in itsentirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present disclosure relates to methods of manufacturing thin filmtransistor (TFT) substrates, and more particularly relates to methods ofmanufacturing TFT substrates having gate wires with double-layeredstructures.

2. Description of the Related Art

A liquid crystal display (LCD) includes a common electrode display panelhaving a color filter and a thin film transistor (TFT) display panelhaving a TFT array. The common electrode and TFT display panels areopposite to and face each other, and are attached to each other by aseal line disposed therebetween. A liquid crystal layer is formed in apredetermined gap created between the two panels. As described above, anLCD generally includes two substrates, each having an electrode formedon an inner surface thereof, and a liquid crystal layer interposedbetween the two substrates. In an LCD, a voltage is applied to theelectrode to rearrange liquid crystal molecules and control an amount oflight transmitted through the liquid crystal layer. Since an LCD is anon-emissive device, a backlight module is required for supplying asource light for a TFT of the LCD. Transmittance of the source lightsupplied from the backlight module is controlled according to thealigned states of liquid crystals.

In general, a gate wire and a data wire including source/drain areformed on the TFT substrate for use in the LCD. Here, the gate and datawires each may be a single layer, or they may have a double-layered or atriple-layered structure such as to prevent the gate and data wires frombeing over-etched in a subsequent etching process. For example, the gatewire generally may have a double-layered structure made of a chromium(Cr) layer and an aluminum (Al) layer.

A process of forming the gate wire will now be described briefly. First,chromium and aluminum are sequentially deposited on a glass substrate toform a double-layered stack on the glass substrate, followed byperforming exposing and developing the formed double-layered stack usinga photo mask to form a pattern. Then, wet etching is performed forsequentially etching the upper aluminum (Al) layer and the lowerchromium (Cr) layer, giving a wire corresponding to the mask pattern.

When the upper aluminum (Al) layer and the lower chromium (Cr) layer arewet etched using the mask during formation of the gate wire, a skewphenomenon may occur, so that a width of a chromium gate wire is reducedcompared to a width of an aluminum gate wire. The skew phenomenon may becaused by an undercut problem. Defects in an LCD, such as horizontalstripes, result from the undercut problem occurring at the lowerchromium (Cr) layer.

One conventional way to avoid such defects is to perform a photo-etchprocess on each layer independently, or to sequentially etch an upperaluminum (Al) layer and a lower chromium (Cr) layer, followed by etchingthe upper aluminum (Al) layer once more. In the former case, however,the number of masks used in the process increases, which increases themanufacturing cost. In the latter case, that is, when the upper aluminum(Al) layer is etched twice, adhesion between an upper photo resist (PR)and the upper aluminum (Al) layer is poor, so that a gate wire having auniform pattern cannot be attained.

SUMMARY OF THE INVENTION

The present disclosure provides a method of manufacturing a thin filmtransistor substrate that can prevent a gate wire from being undercutwhen the gate wire is formed as a double-layered stack. The presentdisclosure also provides a thin film transistor substrate manufacturedby the method. The above and other features and aspects of the presentdisclosure will become clear to those skilled in the art upon review ofthe descriptions that follow.

According to an aspect of the present disclosure, there is provided amethod of manufacturing a thin film transistor substrate. The methodincludes forming a first metal layer made of at least one low resistancematerial selected from the group consisting of Al, AlNd, Cu, and Ag,forming a second metal layer made of at least one heat-resistant,etch-resistant material selected from the group consisting of Cr, CrNx,Ti, Mo, and MoW on the first metal layer, forming an etch mask on thesecond metal layer, sequentially etching the second metal layer and thefirst metal layer using the etch mask, and forming a second metal layerpattern and a first metal layer pattern, respectively, and selectivelyre-etching the second metal layer pattern using the etch mask to make awidth of the second metal layer pattern smaller than or substantiallyequal to a width of the first metal layer pattern, and finallycompleting a gate wire.

According to another aspect of the present disclosure, there is provideda thin film transistor (TFT) substrate comprising a plurality of gatewires formed on an insulating substrate, the plurality of gate wireseach including a first metal layer pattern made of at least one lowresistance material selected from the group consisting of Al, AlNd, Cu,and Ag, and a second metal layer pattern made of at least oneheat-resistant, etch-resistant material selected from the groupconsisting of Cr, CrNx, Ti, Mo, and MoW on the first metal layerpattern, wherein a width of the second metal layer pattern is smallerthan or substantially equal to a width of the first metal layer pattern,a semiconductor pattern formed on the gate wires, a plurality of datawires each including source/drain electrodes separately formed on thesemiconductor pattern, a TFT connected to the data wire and the gatewire, a passivation layer on the data wire, and a pixel electrode formedat a pixel area defined by the gate wire and the data wire.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and aspects of the present disclosure willbecome more apparent by describing in detail preferred embodimentsthereof with reference to the attached drawings, in which:

FIG. 1 is a layout view of a thin film transistor (TFT) substrateaccording to an embodiment of the present disclosure;

FIG. 2 is a cross-sectional view of a thin film transistor (TFT)substrate taken along the line I-I′ shown in FIG. 1;

FIG. 3 is a cross-sectional view of a thin film transistor (TFT)substrate taken along the line II-II′ shown in FIG. 1;

FIGS. 4A through 11B are cross-sectional views of stages in a method ofmanufacturing the TFT substrate shown in FIG. 1; and

FIGS. 12A through 12F are cross-sectional views of stages in a method offorming a gate wire according to an embodiment of the presentdisclosure.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Features and aspects of the present disclosure, and methods ofaccomplishing the same, may be understood more readily with reference tothe following detailed description of preferred embodiments and theaccompanying drawings. The present invention may, however, be embodiedin many different forms and should not be construed as being limited tothe embodiments set forth herein. Rather, these embodiments are providedso that this disclosure will be thorough and complete and will fullyconvey the concept of the invention to those skilled in the art, and thepresent invention will only be defined by the appended claims. Likereference numerals may refer to like elements throughout thespecification.

A TFT substrate will now be described in greater detail with referenceto FIGS. 1 through 3. FIG. 1 is a layout view of a thin film transistor(TFT) substrate according to an embodiment of the present disclosure;FIG. 2 is a cross-sectional view of a thin film transistor (TFT)substrate taken along the line I-I′ shown in FIG. 1; and FIG. 3 is across-sectional view of a thin film transistor (TFT) substrate takenalong the line II-II′ shown in FIG. 1.

A gate wire (22, 24, 26) and a storage electrode line 28 are formed onan insulating substrate 10. The gate wire (22, 24, 26) includes a gateline 22 extending in a transverse direction, a gate line pad 24,connected to an end of the gate line 22, receiving a gate signal from anexternal source and transmitting the received gate signal to the gateline 22, and a gate electrode 26 of a TFT, which is connected to thegate line 22.

The storage electrode line 28 overlaps with a storage capacitorconductor pattern 68 connected with a pixel electrode 82, forming astorage capacitor that enhances a charge storage capacitor of a pixel.When a storage capacitor generated by overlapping of the pixel electrode82 and the gate line 22 is sufficient, formation of the storageelectrode line 29 may be omitted. Generally, a voltage, the same levelof which is applied to a common electrode of a common electrode displaypanel, is applied to the storage electrode line 28.

Here, the gate wire (22, 24, 26) and the storage electrode line 28 maybe formed as a single layer made of a metal or as a double-layered stackconsisting of a lower inorganic layer and an upper organic layer. Oneexample of the gate wire (22, 24, 26) having such a double-layered stackand the storage electrode line 28 will be described in the followingdescription.

When the gate wire (22, 24, 26) is formed as a double-layered stack, afirst metal layer and a second metal layer are sequentially formed on aglass substrate. Here, the first metal layer may be made of Al, AlNd,Cu, or Ag, and the second metal layer may be made of Cr, CrNx, Ti, Mo,or MoW. A gate insulating layer 30 made of silicon nitride (SiNx) isformed on and cover the gate wire (22, 24, 26) and the storage electrodeline 28.

A semiconductor pattern 42, 48 made of a semiconductor such ashydrogenated amorphous silicon (a-Si) is formed on the gate insulatinglayer 30. An ohmic contact layer 55, 56, 58 made of a material like n+hydrogenated amorphous silicon heavily doped with n-type impurities suchas silicide are formed on the semiconductor pattern 42, 48.

A data wire (62, 64, 65, 66, 68) is formed on the ohmic contact layer55, 56, 58. The data wire (62, 64, 65, 66, 68) includes a plurality ofdata line units 62, 65 and 68, a plurality of drain electrodes 66 forTFTs, and a plurality of storage capacitor conductors 64. Each of thedata line units 62, 65 and 68 includes a data line 62 extending in thelongitudinal direction, a data line pad 68 connected to one end of thedata line 62 to receive image signals from an external device, and aplurality of source electrodes 65 of TFTs branched from the data line62. Each drain electrode 66 is separated from the data line units 62, 65and 68 and placed opposite to the corresponding source electrode 65 withrespect to the corresponding gate electrode 26 or the channel area “C”of the TFT. The storage capacitor conductors 64 are placed over thestorage electrode lines 28. In the absence of the storage electrodelines 28, the storage capacitor conductors 64 are also omitted.

The ohmic contact layer 55, 56, 58 reduces the contact resistancebetween the underlying semiconductor pattern 42, 48 and the overlyingdata wire (62, 64, 65, 66, 68), and has substantially the same shape asthe data wire (62, 64, 65, 66, 68). That is, the ohmic contact layer 55,56, 58 includes a plurality of data-line ohmic contact layers 55 havingsubstantially the same shapes as the data line units 62, 68 and 65, aplurality of drain-electrode ohmic contact layers 56 havingsubstantially the same shapes as the drain electrodes 66, and aplurality of storage-capacitor ohmic contact layers 58 havingsubstantially the same shapes as the storage capacitor conductors 64.

Meanwhile, the semiconductor pattern 42, 48 has substantially the sameshape as the data wire (62, 64, 65, 66, 68) and the ohmic contact layer55, 56, 58 except for the TFT channel area “C”. Specifically, thesemiconductor pattern 42, 48 includes a plurality of storage-capacitorsemiconductor patterns 48 having substantially the same shapes as thestorage capacitor conductors 64 and the storage-capacitor ohmic contactlayer 58, and a plurality of TFT semiconductor patterns 42, which haveslightly different shapes from the remainders of the data wire and theohmic contact pattern. That is, the source and the drain electrodes 65and 66 are separated from each other at the TFT channel area “C”, wherethe data-line ohmic contact layer 55 and the drain-electrode ohmiccontact layer 56 are also separated from each other. However, the TFTsemiconductor patterns 42 continue to proceed there withoutdisconnection to form TFT channel area “C”.

A side wall formed by the semiconductor pattern 42, 48, the ohmiccontact layer 55, 56, 58 and the data wire (62, 64, 65, 66, 68) has animproved profile. A passivation layer 70 is formed on the data wire (62,64, 65, 66, 68). The passivation layer 70 preferably includes a SiNxlayer, an a-Si:C:O layer or an a-Si:O:F layer deposited by PECVD (a lowdielectric CVD layer), or an organic insulating layer. The passivationlayer 70 has a plurality of contact holes 72, 76 and 78 exposing thestorage capacitor conductors 64, the drain electrodes 66 and the dataline pads 68. The passivation layer 70 together with the gate insulatinglayer 30 is further provided with a plurality of contact holes 74exposing the gate line pads 24.

A pixel electrode 82, receiving an image signal from the TFT andgenerating an electric field in cooperation with an electrode of anupper panel, is formed on the passivation layer 70. The pixel electrode82 is formed of a transparent conductive material such as ITO and IZO.The pixel electrode 82 is physically and electrically connected to thedrain electrode 66 through the contact hole 76 to receive the imagesignal. The pixel electrode 82 overlaps the neighboring gate line 22 andthe adjacent data line 62 to enlarge the aperture ratio, but theoverlapping may be omitted. The pixel electrode 82 may also be connectedto the storage capacitor conductor 64 through the contact hole 72 totransmit the image signal to the conductor 64. Meanwhile, a plurality ofauxiliary gate line pads 86 and a plurality of auxiliary data line pads88 are formed on the gate line pads 24 and the data line pads 68 to beconnected thereto through the contact holes 74 and 78, respectively. Theauxiliary gate line pads 86 and the auxiliary data line pads 88compensate the adhesiveness of the gate line pads 24 and 68 to externalcircuit devices and protect the pads 24 and 68. The auxiliary gate linepads 86 and the auxiliary data line pads 88 are not requisites but maybe introduced in a selective manner.

A method of manufacturing the TFT substrate according to an embodimentof the present disclosure will be now described in detail with referenceto FIGS. 4A through 12F.

FIGS. 4A through 11B are cross-sectional views of stages in a method ofmanufacturing the TFT substrate shown in FIG. 1, and FIGS. 12A through12F are cross-sectional views of stages in a method of forming a gatewire (22, 24, 26) shown in FIGS. 4A and 4B.

Referring first to FIGS. 4A and 4B, a gate wire (22, 24, 26), includinga gate line 22, a gate electrode 26, and a gate line pad 24, and astorage electrode line 28, is deposited on an insulating substrate 10. Aprocess of the gate wire (22, 24, 26) will later be described withreference to FIGS. 12A through 12F.

To form the gate wire (22, 24, 26), a conductor for forming a gate wireis first stacked on the insulating substrate 10. Here, the conductor maybe as a single layer made of aluminum or may be formed as a doublelayered stack consisting of a first metal layer 220 a and a second metallayer 220 b.

When the conductor is formed as a double layered stack, as shown in FIG.12A, the first metal layer 220 a and the second metal layer 220 b aresequentially formed on the insulating substrate 10. Here, the firstmetal layer 220 a may be made of a low resistance material such as Al,AlNd, Cu, or Ag, and the second metal layer 220 b may be made of aheat-resistant, etch-resistant material such as Cr, CrNx, Ti, Mo, orMoW. The second metal layer 220 b made of such a heat-resistant,etch-resistant material. A material as stated above is well adhered to aphotoresist layer 100 to be formed in a subsequent process, therebyproviding for a uniform pattern when the second metal layer 220 b issecondarily etched. An exemplary embodiment in which the first metallayer 220 a is made of aluminium and the second metal layer 220 b ismade of chromium will be illustrated in the following description.

When the second metal layer 220 b is made of Cr, a CrNx layer ispreferably formed thereon to a predetermined thickness. The CrNx layerformed on the second metal layer 220 b, together with contact holes anda transparent electrode to be formed in a subsequent step, reducescontact resistance between the second metal layer 220 b and thetransparent electrode.

As described above, if the conductor consisting of the first metal layer220 a and the second metal layer 220 b is stacked on the insulatingsubstrate 10, a photoresist layer is coated on the second metal layer220 b for being patterned by photolithography and developed, therebyforming an etch mask on the second metal layer 220 b, as shown in FIG.12B.

Referring to FIGS. 12C and 12D, the second metal layer 220 b and thefirst metal layer 220 a are sequentially etched using the etch mask toform a second metal layer pattern 22 b and a first metal layer pattern22 a. That is, the use of the etch mask enables the second metal layerpattern 22 b and the first metal layer pattern 22 a to be formed fromthe second metal layer 220 b and the first metal layer 220 a throughetching. Here, the second metal layer 220 b and the first metal layer220 a may be patterned by wet etching. In addition, the etch mask may beremoved after removing the second metal layer 220 b.

Alternatively, the second metal layer 220 b and the first metal layer220 a may be simultaneously patterned using the etch mask. Here, thesecond metal layer 220 b and the first metal layer 220 a may bepatterned by dry etching.

In this case, after forming the second metal layer pattern 22 b and thefirst metal layer pattern 22 a, the second metal layer pattern 22 b maybe selectively re-etched using an etch mask, which makes a width of thesecond metal layer pattern 22 b smaller than or equal to a width of thefirst metal layer pattern 22 a. For example, as shown in FIG. 12E, it ispreferable that a width of the second metal layer pattern 22 b besmaller than a width of the first metal layer pattern 22 a. Then, theetch mask remaining on the second metal layer pattern 22 b is removed,thereby finally completing the gate wire (22, 24, 26) having a portionof the second metal layer pattern 22 b that is made thinner than thefirst metal layer pattern 22 a, as shown in FIG. 12F. Here, it ispreferable that a distance between a sidewall of the first metal layerpattern 22 a and a sidewall of the second metal layer pattern 22 b beequal to or less than 1 μm.

After the gate wire (22, 24, 26) and the storage electrode line 28 areformed on the insulating substrate 10, as shown in FIGS. 5A and 5B, agate insulating layer 30, a semiconductor layer 40 and an ohmic contactlayer 50 are sequentially stacked on the resultant structure by chemicalvapor deposition (CVD). Then, sputtering is performed to form aconductive layer 60 for a data wire. Here, the conductive layer 60 for adata wire may be formed as a single layer made of molybdenum (Mo) to athickness of, for example, about 3000 Å to about 4000 Å. Alternatively,the conductive layer 60 for a data wire may have a double-layeredstructure including a molybdenum (Mo) layer and an aluminum (Al) layer,although it is not limited thereto.

A photoresist film 110 is coated on the conductive layer 60 to athickness of 1 to 2 μm. Thereafter, the photoresist film 110 is exposedto light through a mask and is developed to form a photoresist pattern(112 and 114) having a plurality of first portions 114 and a pluralityof second portions 112, as shown in FIGS. 6A and 6B. Each of the firstportions 114 of the photoresist pattern (112 and 114) is located on thechannel area “C” of a TFT, which is placed between a source electrode 65and a drain electrode 66. Each of the second portions 112 is located ona data wire area “A” located at a place where a data wire (62, 64, 65,66, 68) will be formed. All portions of the photoresist film 110 on theremaining areas “B” are removed, and the first portions 114 are made tobe thinner than the second portions 112. Here, the ratio of thethickness of the first portion 114 on the channel area “C” and thesecond portion 112 on the data wire area “A” is adjusted depending onprocess conditions of subsequent etching steps, and it is preferablethat the thickness of the first portion 114 is equal to or less thanabout a half of that of the second portion 112, for example, equal to orless than 4,000 Å.

As described above, the position-dependent thickness of the photoresistpattern (112 and 114) is obtained by several techniques. A slit pattern,a lattice pattern or a translucent film is provided on the mask in orderto adjust the light transmittance in the data wire area “A”.

When using a slit pattern, it is preferable that a width of the slitsand a gap between the slits is smaller than the resolution of an exposerused for the photolithography. In a case of using a translucent film,thin films with different transmittances or different thickness may beused to adjust the transmittance on the masks.

When a photoresist film is exposed to light through such a mask,polymers of a portion directly exposed to the light are almostcompletely decomposed, and those of a portion exposed to the lightthrough a slit pattern or a translucent film are not completelydecomposed because the amount of a light irradiation is small. Thepolymers of a portion of the photoresist film blocked by alight-blocking film provided on the mask are hardly decomposed. Afterthe photoresist film is developed, the portions containing the polymers,which are not decomposed, remains. At this time, the thickness of theportion with less light exposure is thinner than that of the portionwithout light exposure. Since too long an exposure time decomposes allthe molecules, it is necessary to adjust the exposure time.

The first portion 114 of the photoresist pattern (112 and 114) may beobtained using reflow. That is, the photoresist film is made of areflowable material and exposed to light through a normal mask havingopaque and transparent portions. The photoresist film is then developedand subject to reflow such that portions of the photoresist film flowsdown onto areas without photoresist, thereby forming the thin firstportion 114.

Next, as shown in FIGS. 7A and 7B, the ohmic contact layer 50 is exposedby removing the conductive layer 60 with the remaining areas “B” left onthe channel area “C”. Here, wet etching may be performed. Preferably,etching is performed under the condition that the conductive layer 60 isetched but the photoresist pattern (112 and 114) is hardly etched. Then,as shown in FIGS. 8A and 8B, the exposed portion of the ohmic contactlayer 50 left on the remaining areas “B” and the underlyingsemiconductor layer 40 are etched to be removed together with the firstportion 114 of the photoresist film. Here, the photoresist pattern (112and 114), the ohmic contact layer 50 and the semiconductor layer 40 aresimultaneously etched. It is noted that the amorphous silicon layer andthe intermediate layer have no etching selectivity. The etching may beperformed under the condition that the gate insulating layer 30 may notbe etched. Particularly, the etching ratios of the photoresist pattern(112 and 114) and the semiconductor layer 40 may be substantially equalto each other. For example, the film and the layer are etched tosubstantially the same thickness using a gas mixture of SF₆ and HCl or agas mixture of SF₆ and O₂. For the equal etching ratios of thephotoresist pattern (112 and 114) and the semiconductor layer 40, thethickness of the first portion 114 is preferably equal to or less thanthe sum of the thicknesses of the semiconductor layer 40 and the ohmiccontact layer 50. In this way, the first portion 114 on the channel area“C” is removed to expose the source/drain conductor pattern 67, and theohmic contact layer 50 and the semiconductor layer 40 on the remainingareas “B” are removed to expose the underlying portions of the gateinsulating layer 30.

Meanwhile, the second portions 112 on the data wire areas “A” are alsoetched to have reduced thickness. In this step, the formation ofsemiconductor patterns 42 and 48 is completed. Reference numerals 57 and58 indicate an ohmic contact layer underlying the source/drain conductorpattern 67 and an ohmic contact layer underlying a storage capacitorconductor pattern 64, respectively. Subsequently, residue of thephotoresist remaining on the source/drain conductor pattern 67 on thechannel area “C” is removed by ashing.

Next, the source/drain conductor pattern 67 on the channel area “C” andthe underlying portions of the ohmic contact layer 57 are etched to beremoved. Here, wet etching is applied to etch the source/drain conductorpattern 67 and the ohmic contact layer 57. In addition, as shown in FIG.9B, top portions of a semiconductor pattern 42 may be removed to causethickness reduction, and second portions 112 of a photoresist pattern isetched to a predetermined thickness. In this way, as shown in FIGS. 9Aand 9B, the source and the drain electrodes 65 and 66 are separated fromeach other while completing the formation of the data wire (62, 64, 65,66, 68) and the underlying ohmic contact layer 55, 56, 58.

Finally, the second portions 112 remaining on the data wire areas “A”are removed. However, the removal of the second portions 112 may be madebetween the removal of the portions of the source/drain conductorpattern 67 on the channel area “C” and the removal of the underlyingportions of the ohmic contact layer 57.

Next, as shown in FIGS. 10A and 10B, a passivation layer 70 is formed bygrowing a a-Si:C:O film or an a-Si:O:F film by chemical vapor deposition(“CVD”), by coating an organic insulating film. Subsequently, as shownin FIGS. 11A and 11B, the passivation layer 70 is photo-etched togetherwith the gate insulating layer 30 to form contact holes 76, 74, 78 and72 exposing the drain electrode 66, the gate line pad 24 and the dataline pad 68 and the storage capacitor conductor pattern 64,respectively.

Finally, referring back to FIGS. 1 through 3, an ITO layer or an IZOlayer is deposited and photo-etched to a plurality of pixel electrodes82 each connected to the drain electrode 66 and the storage capacitorconductor pattern 64, a plurality of auxiliary gate line pads 86 and aplurality of auxiliary data line pads 88 each connected to the gate linepad 24 and the data line pad 68, respectively. A pre-heating processusing nitrogen gas is preferably performed before depositing ITO or IZO.This is required for preventing the formation of metal oxides on theexposed portions of the metal layers 24, 64, 66 and 68 through thecontact holes 72, 74, 76 and 78.

Thus, an exemplary embodiment TFT substrate of the present disclosureand an exemplary embodiment method of manufacturing the same have beendescribed above. According to these exemplary embodiments, aftersequentially depositing a chromium (Cr) layer and an aluminum (Al)layer, the chromium (Cr) layer is etched twice, thereby preventingconductor layers for data and gate wires from being undercut andultimately preventing defects of an image when an LCD displays an image.

While the present invention has been particularly shown and describedwith reference to exemplary embodiments thereof, it shall be understoodby those of ordinary skill in the pertinent art that various changes inform and details may be made therein without departing from the spiritand scope of the present invention as defined by the following claims.Therefore, it is to be understood that the above-described embodimentshave been provided only in a descriptive sense, and must not beconstrued as placing any limitation on the scope of the invention.

1. A thin film transistor (TFT) substrate comprising: a plurality ofwires formed on an insulating substrate, the plurality of wires eachincluding a first metal layer pattern made of at least one lowresistance material selected from the group consisting of aluminum (Al),aluminum neodymium (AlNd), copper (Cu), and silver (Ag), a second metallayer pattern comprising chromium (Cr) on the first metal layer pattern,and a third metal layer pattern comprising chromium nitride (CrNx) onthe second metal layer pattern, wherein a width of the second metallayer pattern is smaller than or substantially equal to a width of thefirst metal layer pattern.
 2. The TFT substrate of claim 1, wherein theplurality wires are gate wires.
 3. The TFT substrate of claim 2, furthercomprising: a semiconductor pattern formed on the gate wires; aplurality of data wires each including source/drain electrodesseparately formed on the semiconductor pattern; a TFT connected to thedata wire and the gate wire; a plurality of passivation layers eachformed on the data wire; and a plurality of pixel electrodes each formedat a pixel area defined by the gate wire and the data wire.
 4. The TFTsubstrate of claim 1, wherein a distance between a sidewall of the firstmetal layer pattern and a sidewall of the second metal layer pattern isequal to or less than 1 μm.
 5. The TFT substrate of claim 1, wherein thethird metal layer pattern has a thickness of 200 Å or less.
 6. The TFTsubstrate of claim 1, wherein a width of the third metal layer patternis smaller than or substantially equal to a width of the first metallayer pattern.